The invention relates to a circuit and technique for increasing the slew rate of an amplifier.
The term xe2x80x9cslew ratexe2x80x9d of an amplifier is a measure of how fast the amplifier can charge up a large capacitor that is connected to an output conductor of the amplifier in response to a very rapid increase or decrease (such as a step function increase or decrease) of the input voltage applied to the amplifier. A high slew rate generally is a desirable characteristic of an amplifier, especially an operational amplifier, and especially a high-speed CMOS operational amplifier.
The slew rate of an amplifier generally is equal to the smaller of the tail current sources and floating current sources, divided by the sum of the compensation capacitance required and the parasitic capacitance of the output transistor. One technique for increasing the slew rate of an amplifier is to increase the bias current of the input stage, but that has a tendency to increase the bandwidth of the amplifier. That leads to a requirement to increase the compensation capacitance of the amplifier to improve circuit stability, and that tends to decrease the slew rate.
The article xe2x80x9cA Class-AB High-Speed Low-Power Operational Amplifier in BiCMOS Technologyxe2x80x9d, by Subhajit Sen and Bosco Leung, IEEE Journal of Solid-State Circuits, Volume 31, No. 9, September 1986 describes a BiCMOS operational amplifier designed to have very high transconductance, a high slew rate, and a fast small-signal-settling response. The described structure has the disadvantage that it requires use of either bipolar integrated circuit manufacturing technology or BiCMOS manufacturing technology, both of which are substantially more costly than standard CMOS manufacturing technology. The circuit described has the further shortcoming of an undesirably narrow common-mode voltage range.
U.S. Pat. Nos. 4,783,637, 5,512,859 and 5,510,754 disclose amplifiers designed to have high slew rates.
Until now, there have been very few high-speed CMOS operational amplifiers commercially available. This is because until very recently the channel lengths of CMOS transistors that could be readily manufactured using reasonably low-cost CMOS integrated circuit manufacturing processes have not been sufficiently short (i.e., less than about 0.7 microns) to allow CMOS operational amplifiers to compete effectively with high-speed bipolar operational amplifiers manufactured using standard bipolar integrated circuit manufacturing processes.
Thus, there has long been a need for an inexpensive, high-speed, high slew rate integrated circuit operational amplifier which has not been satisfied prior to the previous invention. Especially, there has been need for a low-cost, low voltage CMOS operational amplifier which operates as fast as, and with slew rates as high as, prior bipolar integrated circuit amplifiers.
Accordingly, it is an object of the invention to provide an inexpensive, high-speed integrated circuit operational amplifier having a high slew rate.
It is another object of the invention to provide an inexpensive, high-speed, high-slew-rate integrated circuit operational amplifier which does not require use of a bipolar integrated circuit manufacturing process or a BiCMOS integrated circuit manufacturing process.
Is another object of the invention to increase the slew rate of a high-speed integrated circuit operational amplifier without increasing the quiescent bias current thereof.
It is another object of the invention to provide an inexpensive, high-speed, high-slew-rate integrated circuit operational amplifier which provides an improvement in the amount of nonlinear distortion of high-speed signals, compared to that of prior bipolar operational amplifiers having high slew rates.
Is another object of the invention to provide a low voltage CMOS amplifier that is as fast as a traditional high-speed, high-voltage, high-slew-rate bipolar integrated circuit amplifier.
It is another object of the invention to prevent instability in a high slew rate CMOS amplifier by accurately controlling the amount of slew boost current therein.
Briefly described, and in accordance with one embodiment thereof, the invention provides an operational amplifier which includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control-circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second inputs of a second unbalanced differential amplifier (32). If the the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier (31), the magnitude of a turn-on voltage of the pull-down transistor (M12) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased, both in response to an output voltage produced by the first unbalanced differential amplifier (31). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier (32), then the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M12) is simultaneously decreased, both in response to an output voltage produced by the second unbalanced differential amplifier (32).
In one embodiment of the invention, an operational amplifier (1) includes a differential input stage (30) having first (2) and second (3) input conductors and first (4) and second (5) output conductors and a class AB output stage (20). The class AB output stage includes a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11). The class AB output stage (20) also includes a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A gain stage (24) includes an input coupled to at least one of the first (4) and second (5) output conductors of the differential input stage (30). The gain stage (24) has an output coupled to the second terminal (15) of the class AB control circuit (11). In accordance with the present invention, a slew rate boost circuit (10) includes a first unbalanced differential amplifier (31) having a first input coupled to the first input conductor (2) and a second input coupled to the second input conductor (3) and first (6) and second (7) output conductors. The slew rate boost circuit (10) also includes a second unbalanced differential amplifier (32) having a first input coupled to the first input conductor (2) and a second input coupled to the second input conductor (3) and first (8) and second (9) output conductors. A first boost amplifier (22) includes first and second inputs coupled to the first (6) and second (7) outputs, respectively, of the first unbalanced amplifier (31), and a second boost amplifier (21) having first and second inputs coupled to the first (8) and second (9) outputs, respectively, of the second unbalanced amplifier (32). First (M5) and second (M10) transistors each have a gate coupled to an output of the first boost amplifier (22). The first transistor (M5) has a source coupled to the second output (7) of the first unbalanced amplifier (31) and a drain coupled to the first supply voltage (VDD). The second transistor (M10) has a source coupled to the second supply voltage (GND) and a drain coupled to the second terminal (15) of the class AB control circuit (11). Third (M6) and fourth (M7) transistors each have a source coupled to the first supply voltage (VDD) and a gate coupled to an output of the second boost amplifier (21). The third transistor (M6) has a drain coupled to the first output (8) of the second unbalanced amplifier (32). The fourth transistor (M7) has a drain coupled to the first terminal of the class AB control circuit (11).